A method has been proposed by which, in a system that includes an arithmetic processing apparatus, a main storage apparatus, and an input/output apparatus, a test of the input/output apparatus is executed using a test processor that in operation when the arithmetic processing apparatus is not in operation (for example, see Japanese Laid-open Patent Publication No. 63-93048).
In addition, an information processing apparatus has been proposed that connects a main memory control apparatus in which a central processing unit (CPU) is connected to a service processor, to an input/output apparatus, through a channel processor and an input/output control apparatus using a plurality of routes.
In such a kind of the information processing apparatus, when the service processor specifies a route and checks the state of the input/output apparatus, the normality of the route is diagnosed when the information processing apparatus is in operation (for example, see Japanese Laid-open Patent Publication No. 3-214341).
However, in a case in which the test processor that is in operation when the arithmetic processing apparatus is not in operation executes a test of the input/output apparatus, the processing by the arithmetic processing apparatus is terminated in the middle of the test of the input/output apparatus. In addition, when the central processing unit and the service processor are connected to a channel processor through the main memory control apparatus, the range in which the service processor may perform diagnosis is merely limited to the connection route.
An object of a switch apparatus, an information processing apparatus, a control method of the information processing apparatus, and a control program of the information processing apparatus that are discussed herein is to minimize the impact on the processing performance of an arithmetic processing apparatus, and to execute a test of an input/output apparatus that is connected to the arithmetic processing apparatus.